In some process flows for semiconductor devices having metal-oxide-semiconductor (MOS) transistors at the contact level there is a need for two or more contact masking levels due to pattern density and/or stop layers differences between different regions of the die, such as in higher pattern density “cell areas” and lower density “gate areas”. FIG. 1 is a simplified top view depiction of a portion of a semiconductor power device 100 formed using a known method for contact etching comprising a substrate 105 having a topside semiconductor surface (e.g., silicon surface) 106 having a plurality of vertical power MOS transistors. Inter-layer dielectric (ILD) and metal is omitted in FIG. 1 to show the hard mask layer 133 on the gate stacks and the various MOS transistor contacts.
The vertical power MOS transistors each have a gate contact 111 shown in the gate area 110 to gate lines 115, which are polysilicon gate contacts in the case of polysilicon gates, as well as a semiconductor contact 121 in the cell area 120 between adjacent gate lines 115. Although the gate lines 115 are shown as being linear throughout, in a practical power device the gate lines are not linear throughout. The gate lines 115 are each gate stacks including the hard mask layer 133 shown on a gate electrode on a gate dielectric (both gate electrode and gate dielectric not shown). The hard mask layer 133 on each gate line 115 has a substantially constant thickness (typically a range of <1%), set by the local uniformity provided by the hard mask layer deposition tool. The semiconductor contact 121 provides either a source or a drain for the vertical power MOS transistors, with the other of the source and the drain provided by a bottomside contact 107 to the substrate 105. In a practical power device, there are a very large number of power MOS devices in parallel so that there are a large number of semiconductor contacts 121 in the cell area 120 and a large number of gate contacts 111 in the gate area 110.
At what may be referred to as the “source” contact mask level, the gate area 110 is fully masked (i.e. covered, such as by a photoresist), and the source contact etch reaches the semiconductor surface 106 in the cell area 120. A Ti/TiN or other suitable diffusion barrier layer comprising a refractory metal is then typically added to the exposed semiconductor surface, followed by a layer of inter-layer dielectric (ILD) over the respective semiconductor die on the wafer.
A second contact level that may be referred to as the “drain” contact mask level then follows. At this level, openings in both the gate area 110 and in the cell area 120 are formed in photoresist. This etch is required to etch through ILD and the hard mask (typically Si3N4; silicon nitride) over the gate area 110 to reach a metal silicide (e.g., WSi2) on the gate contacts 111 in the gate area 110, while stopping on the TiN barrier over the semiconductor contacts 121 in the cell area 120.
It is a challenge to provide an etch process consistently able to etch through the gate area hard mask layer (e.g., Si3N4) to reach the metal silicide (e.g., WSi2) on the gate contacts 111 in the gate area 110 to allow contact thereto, while stopping on the TiN or other barrier layer on the semiconductor contacts 121 in the cell area 120 without substantial barrier layer thinning during the same etch process. This challenge arises because this etch process needs a high silicon nitride/oxide etch selectivity to etch through the silicon nitride hard mask. Meanwhile, the same etch process needs a low silicon nitride/oxide etch selectivity to land (stop) on the barrier layer (e.g., TiN on Ti) on the semiconductor contacts 121 in the cell area 120. This challenge can result in leaving residual silicon nitride hard mask on the gate contacts 111 in the gate area 110 which causes electrical opens or high resistance contacts, known to result in yield loss.